EDB8164B4PT-1DITF-R datasheet(26/152 Pages) MICRON

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Figure 10: Functional Block Diagram

CS_n

CA[9:0]

Input and Output buffer

Latch circuit

Data control circuit

Column

address

buffer

and

burst

counter

Row

address

buffer

and

refresh

counter

Mode

CK_t

CK_c

CKE

DQS_t

DQS_c

Bank n

Column decoder

Memory cell array

Bank 0

Sense amp.

Note:

1. 512Mb is a 4-bank only.

Simplified State Diagram

The state diagram provides a simplified illustration of allowed state transitions and the

related commands to control them. For a complete definition of the device behavior,

the information provided by the state diagram should be integrated with the truth ta-

bles and timing specification. The truth tables provide complementary information to

the state diagram, they clarify the device behavior and the applied restrictions when

considering the actual state of all the banks.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

Simplified State Diagram

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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