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EDB8164B4PT-1DITF-R 데이터시트(PDF) 84 Page - Micron Technology

부품명 EDB8164B4PT-1DITF-R
상세설명  216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM Features
PDF  152 Pages
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(tZQINIT, tZQCL, or tZQCS). The quiet time on the data bus helps to calibrate output im-
pedance accurately. There is no required quiet time after the ZQRESET command. If
multiple devices share a single ZQ resistor, only one device can be calibrating at any giv-
en time. After calibration is complete, the ZQ ball circuitry is disabled to reduce power
consumption.
In systems sharing a ZQ resistor between devices, the controller must prevent tZQINIT,
tZQCS, and tZQCL overlap between the devices. ZQRESET overlap is acceptable. If the
ZQ resistor is absent from the system, ZQ must be connected to VDD2. In this situation,
the device must ignore ZQ calibration commands and the device will use the default
calibration settings.
Figure 55: ZQ Timings
Notes:
1. Only the NOP command is supported during ZQ calibrations
tZQINIT: ZQ calibration initialization period
tZQCS: ZQ calibration short period
t ZQCL: ZQ calibration long period
tZQRESET: ZQ calibration reset period
216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM
MODE REGISTER WRITE Command
09005aef85eb530a
216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN
84
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.



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