STM32G070CB datasheet(73/93 Pages) STMICROELECTRONICS

73 / 93 page

DS12766 Rev 2

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STM32G070CB/KB/RB

Electrical characteristics

5.3.21

Characteristics of communication interfaces

I2C-bus interface characteristics

The I2C-bus interface meets timing requirements of the I2C-bus specification and user

manual rev. 03 for:



Standard-mode (Sm): with a bit rate up to 100 kbit/s



Fast-mode (Fm): with a bit rate up to 400 kbit/s



Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.

The timings are guaranteed by design as long as the I2C peripheral is properly configured

(refer to the reference manual RM0454) and when the I2CCLK frequency is greater than the

minimum shown in the following table.

Table 58. TIMx(1) characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

-1

tTIMxCLK

fTIMxCLK = 64 MHz

15.625

fEXT

Timer external clock frequency

on CH1 to CH4

-0

fTIMxCLK/2

MHz

fTIMxCLK = 64 MHz

ResTIM

Timer resolution

TIMx

bit

tCOUNTER

16-bit counter clock period

65536

tTIMxCLK

fTIMxCLK = 64 MHz

0.015625

1024

µs

tMAX_COUNT

Maximum possible count with

32-bit counter

65536 × 65536

tTIMxCLK

fTIMxCLK = 64 MHz

67.10

1. TIMx, is used as a general term in which x stands for 1,, 3, 4, 5, 6, 7, 8, 15, 16 or 17.

Table 59. IWDG min/max timeout period at 32 kHz LSI clock(1)

Prescaler divider

PR[2:0] bits

Min timeout RL[11:0]= 0x000

Max timeout RL[11:0]= 0xFFF

Unit

0.125

512

0.250

1024

/16

0.500

2048

/32

1.0

4096

/64

2.0

8192

/128

4.0

16384

/256

6 or 7

8.0

32768

1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an

uncertainty of one RC period.

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