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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STMIPID02 데이터시트(PDF) 5 Page - STMicroelectronics |
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STMIPID02 데이터시트(HTML) 5 Page - STMicroelectronics |
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5 / 50 page  3 Output interface The output interface is used to transfer image data from the STMIPID02 to the host. Features • CCIR601 compliant • 12-bit data with pixel clock, HSYNC and VSYNC (external synchronization signals) • Up to 200 MHz pixel clock, giving a data rate of 1.6 Gbit/s • Programmable polarity of synchronization signals • Tristate output control for multiple camera systems By default, VSYNC envelopes all lines of valid image data. HSYNC is active on all lines including vertical frame blanking period. HSYNC and VSYNC output polarities are programmable. The description and the figures below assume the default polarity. The host uses the rising edge of the PCLK to sample both the data and the synchronization lanes. Since the output data bus is 12 bits wide, for an output stream of less than 12 bits per pixel, the data can be placed on lower or upper bits of the bus. This is controlled by the Mode_Reg1[7] (address 0x14). Table 1. Image format vs. number of bits on output interface Image format received Data type to be programmed in STMIPID02 Number of bits on parallel output of STMIPID02 RAW6 RAW6 6 bits RAW7 RAW7 7 bits RAW8 RAW8 8bits RAW10 RAW10 10 bits RAW12 RAW12 12 bits RAW10 (as 10-6 compressed) RAW6 (with decompression 6-10 enabled) 10 bits RAW10 ( as 10-7) RAW7 (with decompression 7-10 enabled) 10 bits RAW10 (as 10-8) RAW8 (with decompression 8-10 enabled) 10 bits RAW12 (as 12-10) RAW10 (with decompression 10-12 enabled) 12 bits RAW12 (as 12-8) RAW8 (with decompression 8-12 enabled) 12 bits RAW12 (as 12-7) RAW8 (with decompression 7-12 enabled) 12 bits RAW12 (as 12-6) RAW8 (with decompression 6-12 enabled) 12 bits RGB565 RAW8 8 bits RGB888 RAW8 8 bits RGB444 RAW8 8 bits YUV420 8 bits RAW8 8 bits YUV422 8 bits RAW8 8 bits YUV420 10 bits RAW10 10 bits STMIPID02 Output interface DS12803 - Rev 1 page 5/50 |
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