STMIPID02 datasheet(40/50 Pages) STMICROELECTRONICS

부품명	STMIPID02

상세설명	Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer

PDF	50 Pages

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제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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40 / 50 page

11.5.4

Parallel output interface timing

Figure 14. Parallel output interface timing diagram - inverted clock

1/fPCLK

PCLK

D[11:0],

HSYNC, VSYNC

tDV

Valid

Figure 15. Parallel output interface timing diagram - non inverted clock

1/fPCLK

PCLK

D[11:0],

HSYNC, VSYNC

tDV

Valid

Note:

For Non-inverted clock mode, the valid edge to capture is the negative (falling) edge

For RAW6/RAW7 dual lane, the bandwith is limited to 800 Mbps.

Table 16. Parallel output interface timing

Symbol

Description

Conditions

Min.

Typ.

Max.

Unit

fPCLK

PCLK frequency

200

MHz

DPCLK

PCLK duty

cycle

No bypass,

RAW6 dual lane

No bypass,

RAW7 dual lane

No bypass,

RAW7 dual

lane, jittered

clock

50-60

No bypass,

RAW7 single

lane

57.14

Bypass and all

other modes

PCLK rise time,

20 % - 80 %

Load

capacitance, CL

= 50 pF

2.1

tDV

PCLK to output

valid

STMIPID02

AC electrical characteristics

DS12803 - Rev 1

page 40/50

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