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STMIPID02 데이터시트(PDF) 3 Page - STMicroelectronics |
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STMIPID02 데이터시트(HTML) 3 Page - STMicroelectronics |
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3 / 50 page ![]() 1 Block diagram Figure 1. Block diagram SCL SDA EXTCLK CLKP1 CLKN1 DATA1P1 DATA1N1 D[11:0] VSYNC ERROR INT I2C slave SMIA CCP2 RX Clock MIPI CSI-2 RX STMIPID02 Slave clock lane module manager 400kHz 1.2V voltage regulator (LDO) JTAG controller Clock recovery & de-serializer Clock lane control interface logic Slave data lane module Data lane control interface logic MIPI D-PHY RX Protocol DATA2P1 DATA2N1 Data Lane 1.2 80-800Mbps Data Lane 1.1 80-800Mbps Clock Lane 1 40-400MHz HSYNC PCLK (up to 200MHz) Power on reset VDDOUT_LDO 6.0MHz - 27MHz 1V8 12-bit parallel interface @ 200MHz 1V8 Doubles as CCP2 data & clock/strobe inputs XSDN Slave data lane module Data lane control interface logic CLKP2 CLKN2 DATA1P2 DATA1N2 Slave clock lane module Clock lane control interface logic Data Lane 2 80-800Mbps Clock Lane 2 40-400MHz Slave data lane module Data lane control interface logic Doubles as CCP2 data & clock/strobe inputs STMIPID02 Block diagram DS12803 - Rev 1 page 3/50 |
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