TMUX7462F datasheet(26/37 Pages) TI

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8.3.2.2 Powered-Off Protection

The source (Sx) pins of the device remain in the high impedance (Hi-Z) state, and the device performance

remains within the leakage performance specifications when the supplies of TMUX7462F are removed (VDD/ VSS

= 0 V or floating) or at a level that is below the undervoltage (UV) threshold. Powered-off protection minimizes

system design complexity by removing the need to control the system's power supply sequencing. The feature

prevents errant voltages on the input source pins from reaching the rest of the system and maintains isolation

when the system is powering up. Without powered-off protection, signal on the input source pins can back-power

the supply rails through internal ESD diodes and cause potential damage to the system.

A GND reference must always be present to ensure proper operation. Source and drain voltage levels of up to

±60 V are blocked in the powered-off condition.

8.3.2.3 Fail-Safe Logic

Fail-Safe logic circuitry allows voltages on the control input pin (DR) to be applied before the supply pins. This

eliminates the need for power sequencing of the logic signals and protects the device from potential damage.

The control inputs are protected against positive faults of up to +44 V in the powered-off condition, but do not

offer protection against a negative overvoltage condition.

8.3.2.4 Overvoltage Protection and Detection

The TMUX7462F detects overvoltage inputs by comparing the voltage on a source pin (Sx) with the fault

supplies (VFP and VFN). A signal is considered overvoltage if it exceeds the fault supply voltages by the threshold

voltage (VT).

The switch automatically turns OFF and the source pin becomes high impedance to ensures only small leakage

currents flow through the switch when an overvoltage is detected. The drain pin (Dx) behavior can be adjusted

by controlling the drain response (DR) pin in the following ways:

1. DR pin floating or driven above VIH:

If the DR pin is driven about VIH level of the pin, then the drain pin becomes high impedance (Hi-Z) upon

overvoltage fault.

2. DR driven below VIL:

If the DR pin is driven below VIL level of the pin, then the drain pin (Dx) is pulled to the supply that was

exceeded. For example, if the source voltage exceeds VFP, then the drain output is pulled to VFP. If the

source voltage exceeds VFN, then the drain output is pulled to VFN. The pull-up impedance is approximately

40 kΩ, and as a result, the drain current is limited to roughly 1 mA during a shorted load (to GND) condition.

Figure 8-1 shows a detailed view of the how the DR pin controls the output state of the drain pin under a fault

scenario.

VDD

VSS

VFP

VFN

GND

ESD

Protection

Fault

Detection

40 k

Logic

Figure 8-1. Detailed Functional Diagram

VFP and VFN are required fault supplies that set the level at which the overvoltage protection is engaged. VFP can

be supplied from 3 V to VDD, while the VFN can be supplied from VSS to 0 V. If the fault supplies are not available

in the system, then the VFP pin must be connected to VDD, while the VFN pin must be connected to VSS. In this

case, the overvoltage protection then engages at the primary supply voltages VDD and VSS.

TMUX7462F

SCDS394A – MARCH 2021 – REVISED OCTOBER 2021

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