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AD4134 데이터시트(PDF) 39 Page - Analog Devices |
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AD4134 데이터시트(HTML) 39 Page - Analog Devices |
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39 / 92 page ![]() Data Sheet AD4134 CIRCUIT INFORMATION analog.com Rev. 0 | 39 of 92 The interpolation factor depends on the ODR selected. The frac- tional sample rate conversion of the ASRC allows the final ODR to be asynchronous to the sampling clock of the modulator. The output of the ASRC is then decimated by an integer in the digital filter to produce the final ODR. The ASRC only response depends on the ODR selected and has a notch at the value of interpolation factor × ODR frequency. The interpolation factor values for the various ODRs are shown in Table 18. Table 18. Interpolation Factor Values for Different ODR Ranges ODR Range Interpolation Factor Value 750 kSPS to 1.496 MSPS 8 375 kSPS to 749.999 kSPS 16 366.99 SPS to 374.999 kSPS 32 10 SPS to 366.99 SPS 1024 For example, the ASRC response for an ODR of 374 kSPS shows a notch at 32 × 374 kHz = 11.968 MHz, as shown in Figure 72. Figure 72. ASRC Only Response for ODR = 374 kSPS Similarly, the ASRC response for an ODR of 1496 kSPS shows a notch at 8 × 1496 kHz = 11.968 MHz, as shown in Figure 73. Figure 73. Response for ODR of 1496 kSPS The available output data rate range varies based on the digital filter type and the ASRC mode selected (see the Digital Filters section for more information). The ASRC on the AD4134 has the following two modes of opera- tion: ► In master mode, the ODR pin is output and the ODR is set through the pin configuration or a register write. ► In slave mode, the ODR pin is input to the AD4134 and the ODR is set with an external clock source. ASRC Master Mode In master mode, the ASRC resamples the interpolated modulator output at a fixed ratio to the modulator clock (see Figure 74). The ratio is internally calculated based on the user setting of the final ODR. The user can configure the ODR through configuration of the ODR pin in pin control mode or through register configuration in SPI control mode. In ASRC master mode, the ODR pin behaves as an output. It produces a pulse train signal in the frequency of the output data rate. The ADC output data is made available for sampling with respect to the ODR signal. For details of the ASRC master mode output data rate setting, see the ASRC Master Mode section. Figure 74. ASRC Master Mode Functional Diagram |
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