AD4134 datasheet(16/92 Pages) AD

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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 16 of 92

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

AGND5

GND

Ground Reference for Analog Supply Voltage, 5 V.

DNC

Do Not Connect. Do not connect to this pin.

AIN0+

Positive Analog Input to ADC Channel 0.

AIN0−

Negative Analog Input to ADC Channel 0.

AGND5

GND

Ground Reference for Analog Supply Voltage, 5 V.

AIN1+

Positive Analog Input to ADC Channel 1.

AIN1−

Negative Analog Input to ADC Channel 1.

VCM

Common-Mode Voltage Output. The VCM output can be used to provide a common-mode voltage for the analog

front-end circuit. The VCM pin provides a buffered voltage output. The level is fixed to 1/2 of the voltage on the

REFCAP pin in pin control mode, and is programmable in SPI control mode. When driving capacitive loads larger

than 0.2 nF, it is recommended to place a 50 Ω series resistor between the pin and the capacitive load for stability.

REFIN

ADC Reference Filter Input. Use an internal 20 Ω resistor together with an external capacitor on the REFCAP pin to

filter the reference source noise.

REFCAP

ADC Reference Direct Input. Connect this pin to the external reference source for a direct reference input.

Alternatively, connect the reference source to the REFIN pin and place a filter capacitor between the REFCAP pin

and REFGND pin to limit the reference noise bandwidth. See the Reference Input section for more details.

REFGND

GND

ADC Reference Ground Reference.

AIN2+

Positive Analog Input to ADC Channel 2.

AIN2−

Negative Analog Input to ADC Channel 2.

AGND5

GND

Ground Reference for Analog Supply Voltage, 5 V.

AIN3+

Positive Analog Input to ADC Channel 3.

AIN3−

Negative Analog Input to ADC Channel 3.

CLKGND

GND

Clock Management Circuit Ground Reference.

CLKVDD

Clock Management Circuit Power Supply, 1.8 V. This pin is supplied from an external source or internal LDO

regulator. In either case, a decoupling capacitor of 2.2 µF is required between the CLKVDD pin and CLKGND pin.

XTAL2/CLKIN

Input 2 for Internal Crystal Oscillator (XTAL2). Connect an external crystal between the XTAL1 pin and XTAL2/

CLKIN pin for on-chip clock generation.

Clock Input (CLKIN). For operations using an external clock signal, connect this pin to the external clock source.

See the Clock Input section for more details.

XTAL1

Input 1 for Internal Crystal Oscillator. Connect an external crystal between the XTAL1 pin and XTAL2/CLKIN pin

for on-chip clock generation. Leave this pin floating if the device is to operate from a single-ended external clock

signal.

CLKSEL

Clock Source Selection Input. Connect this pin to IOVDD to enable on-chip clock generation from an external

crystal. Connect this pin to IOGND if the clock signal is provided externally on the XTAL2/CLKIN pin.

XCLKOUT

Crystal Oscillator Buffered Output. A buffered clock signal generated by the internal crystal oscillator is available

on this pin. This signal can be used to drive other AD4134 devices working in parallel. The XCLKOUT output is

enabled by default in pin control mode only if the crystal clock option is selected. The XCLKOUT output is disabled

by default in SPI control mode. See the XCLKOUT Output section for more details.

PIN/SPI

Device Configuration Mode Control Input. Tie this pin to IOVDD to enable device configuration through register

access over the SPI. Tie this pin to ground to enable device configuration through the configuration input pins.

MODE

ASRC Mode Of Operation Control Input. Tie this pin to IOVDD for master mode operation. Tie this pin to IOGND for

slave mode operation.

DCLKRATE0/GPIO0

DI/O

DCLK Frequency Control Input 0 in Pin Control Mode (DCLKRATE0). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 0 in SPI Control Mode (GPIO0).

DCLKRATE1/GPIO1

DI/O

DCLK Frequency Control Input 1 in Pin Control Mode (DCLKRATE1). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 1 in SPI Control Mode (GPIO1).

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