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Data Sheet

AD4134

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

DCLKRATE2/GPIO2

DI/O

DCLK Frequency Control Input 2 in Pin Control Mode (DCLKRATE2). When DCLK is configured as an output, tie

this pin to IOVDD or to IOGND to set the frequency ratio between DCLK and the device master clock. See Table 30

for more details.

General-Purpose Input/Output 2 in SPI Control Mode (GPIO2).

RESET

Hardware Asynchronous Reset Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during

normal operation. Pull this pin low to IOGND to force the device into reset. See the Reset section for more details.

PDN

Full Power-Down Mode Control Input, Active Low. Pull this pin to IOVDD through a 10 kΩ pull-up resistor during

normal operation. Pull this pin to IOGND to force the device into full power-down mode. See the Power Modes

section for more details.

PWRMODE/GPIO3

DI/O

Power Mode Selection Input in Pin Control Mode (PWRMODE). Tie this pin to IOVDD for high performance mode.

Tie this pin to IOGND for low power mode.

General-Purpose Input/Output 3 in SPI Control Mode (GPIO3).

EPAD

Exposed Pad. Connect the exposed pad to AGND5.

1 DI is digital input, DI/O is bidirectional digital input/output, DO is digital output, P is power, GND is ground, DNC is do not connect, AI is analog input, and AO is analog

output.

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