STM32WB10CC datasheet(71/110 Pages) STMICROELECTRONICS

71 / 110 page

DS13259 Rev 2

71/110

STM32WB10CC

Electrical characteristics

102

6.3.8

Wakeup time from Low-power modes and voltage scaling



transition times

The wakeup times given in Table 41 are the latency between the event and the execution of

the first user instruction.

The device goes in Low-power mode after the WFE (Wait For Event) instruction.

APB1

RTC

0.940

0.875

µA/MHz

I2C1 independent clock domain

1.95

3.90

I2C1 clock domain

3.75

4.10

LPTIM1 independent clock domain

1.95

2.90

LPTIM1 clock domain

3.45

3.60

TIM2

4.55

4.00

LPTIM2 clock domain

3.45

3.70

LPTIM2 independent clock domain

1.95

3.50

WWDG

0.350

0.625

All APB1 peripherals

15.5

16.0

APB2

AHB to APB2(3)

0.900

1.10

TIM1

6.25

6.10

USART1 independent clock domain

3.05

6.50

USART1 clock domain

6.25

5.50

SPI1

1.25

1.05

ADC1 independent clock domain

0.940

0.600

ADC1 clock domain

0.780

0.600

All APB2 on

14.5

15.5

All peripherals

48.5

45.0

1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).

2. GPIOs consumption during read and write accesses.

3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

Table 40. Peripheral current consumption (continued)

Peripheral

Run

Low-power

run and Sleep

Unit

Table 41. Low-power mode wakeup timings(1)

Symbol

Parameter

Conditions

Typ

Max

Unit

tWUSLEEP

Wakeup time from

Sleep mode



to Run mode

-9

No. of

CPU

cycles

tWULPSLEEP

Wakeup time from



Low-power sleep mode

to Low-power run mode

Wakeup in Flash with memory in power-down

during low-power sleep mode (FPDS = 1 in

PWR_CR1) and with clock MSI = 2 MHz

910

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