STM32WB35CC datasheet(166/193 Pages) STMICROELECTRONICS

166 / 193 page

Electrical characteristics

STM32WB55xx STM32WB35xx

166/193

DS11929 Rev 11

Table 96. SAI characteristics(1)

1. Guaranteed by characterization results.

Symbol

Parameter

Conditions

Min

Max

Unit

fMCLK

SAI main clock output

MHz

fCK

SAI clock frequency(2)

2. APB clock frequency must be at least twice SAI clock frequency.

Master transmitter



2.7 V ≤ VDD ≤ 3.6 V

Voltage Range 1

-23.5

Master transmitter



1.65 V ≤ VDD ≤ 3.6 V

Voltage Range 1

-16

Master receiver



Voltage Range 1

-16

Slave transmitter



2.7 V ≤ VDD ≤ 3.6 V

Voltage Range 1

-26

Slave transmitter



1.65 V ≤ VDD ≤ 3.6 V

Voltage Range 1

-20

Slave receiver



Voltage Range 1

-32

Voltage Range 2

tv(FS)

FS valid time

Master mode



2.7 V ≤ VDD ≤ 3.6 V

-21

Master mode



1.65 V ≤ VDD ≤ 3.6 V

-30

th(FS)

FS hold time

Master mode

tsu(FS)

FS setup time

Slave mode

1.5

th(FS)

FS hold time

Slave mode

2.5

tsu(SD_A_MR)

Data input setup time

Master receiver

tsu(SD_B_SR)

Slave receiver

1.5

th(SD_A_MR)

Data input hold time

Master receiver

6.5

th(SD_B_SR)

Slave receiver

2.5

tv(SD_B_ST) Data output valid time

Slave transmitter (after enable edge)



2.7 V ≤ VDD ≤ 3.6 V

-19

Slave transmitter (after enable edge)



1.65 V ≤ VDD ≤ 3.6 V

-25

th(SD_B_ST) Data output hold time Slave transmitter (after enable edge)

tv(SD_A_MT) Data output valid time

Master transmitter (after enable edge)



2.7 V ≤ VDD ≤ 3.6 V

-18.5

Master transmitter (after enable edge)



1.65 V ≤ VDD ≤ 3.6 V

-25

th(SD_A_MT) Data output hold time Master transmitter (after enable edge)

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