STM8L051F3 datasheet(94/96 Pages) STMICROELECTRONICS

94 / 96 page

Revision history

STM8L051F3

94/96

DS9178 Rev 4

Revision history

Table 54. Document revision history

Date

Revision

Changes

01-Aug-2012

Initial release.

26-Mar-2014

Updated TSS0P20 package information

Updated pin name related to pin1 and 2 inside Table 4: STM8L051F3

pin description

Updated inside Table 10: Option byte addresses OPT5 default factory

of BOR to 0x00

04-Jul-2017

Updated

– All document to refer to specific RPN instead to the whole Value line

when relevant to make content clearer

– Document’s title

– Footnotes were standardized on Section 8: Electrical parameters

– Figure on Features on the cover page

– Section 1: Introduction

– Section 2: Description

– Section 2.2: Ultra-low-power continuum

– Section 8.2: Absolute maximum ratings

– Section 9.3: TSSOP20 package information

– Figure 1: STM8L051F3 block diagram

– Figure 2: STM8L051F3 clock tree diagram

– Figure 5: Pin loading conditions

– Figure 6: Pin input voltage

– Figure 8: Typ. IDD(RUN) vs. VDD, fCPU = 16 MHz

– Figure 9: Typ. IDD(Wait) vs. VDD, fCPU = 16 MHz 1)

– Figure 10: Typ. IDD(LPR) vs. VDD (LSI clock source)

– Figure 11: Typ. IDD(LPW) vs. VDD (LSI clock source)

– Figure 13: LSE oscillator circuit diagram

– Figure 15: Typical LSI frequency vs. VDD

– Figure 16: Typical VIL and VIH vs VDD (high sink I/Os)

– Figure 17: Typical VIL and VIH vs VDD (true open drain I/Os)

– Figure 18: Typical pull-up resistance RPU vs VDD with VIN=VSS

– Figure 19: Typical pull-up current Ipu vs VDD with VIN=VSS

– Figure 29: SPI1 timing diagram - slave mode and CPHA=0

– Figure 30: SPI1 timing diagram - slave mode and CPHA=1(1)

– Figure 34: Typical connection diagram using the ADC

– Figure 35: Maximum dynamic current consumption on VREF+ supply

pin during ADC conversion

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