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SPC572LX 데이터시트(PDF) 32 Page - STMicroelectronics |
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SPC572LX 데이터시트(HTML) 32 Page - STMicroelectronics |
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32 / 112 page ![]() Electrical characteristics SPC572Lx 32/112 DocID027866 Rev 5 Table 17 shows the VERY STRONG configuration output buffer electrical characteristics. TPHL/PLH CC D Propagation delay CL = 25 pF, 4.5 V < VDD_HV_IO < 5.9 V — — 12 ns CL = 25 pF, 3.0 V < VDD_HV_IO < 3.6 V —— 18 CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V —— 20 CL = 50 pF, 3.0 V < VDD_HV_IO < 3.6 V(5) —— 36 1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid for VSIO[VSIO_xx] = 0 2. All values need to be confirmed during device validation. 3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added to calculate total signal capacitance (CTOT = CL + CIN). 4. Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF. 5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_ETH segment when VSIO[VSIO_IF] = 0 Table 16. STRONG configuration output buffer electrical characteristics (continued) Symbol C Parameter Conditions(1) Value(2) Unit Min Typ Max Table 17. VERY STRONG configuration output buffer electrical characteristics Symbol C Parameter Conditions(1) Value(2) Unit Min Typ Max ROH_V CC P PMOS output impedance VERY STRONG configuration VDD_HV_IO = 5.0 V ± 10%, VSIO[VSIO_xx] = 1, IOH = 8 mA 20 40 60 Ω CVDD_HV_IO = 3.3 V ± 10%, VSIO[VSIO_xx] = 0, IOH = 7 mA(3) 30 50 75 ROL_V CC P NMOS output impedance VERY STRONG configuration VDD_HV_IO = 5.0 V ± 10%, VSIO[VSIO_xx] = 1, IOL = 8 mA 20 40 60 Ω CVDD_HV_IO = 3.3 V ± 10%, VSIO[VSIO_xx] = 0, IOL = 7 mA(3) 30 50 75 fMAX_V CC T Output frequency VERY STRONG configuration VDD_HV_IO = 5.0 V ± 10%, CL = 25 pF(4) —— 50 MHz VSIO[VSIO_xx] = 1, CL = 15 pF(3),(4) —— 50 |
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