SPC58EEX datasheet(125/154 Pages) STMICROELECTRONICS

125 / 154 page

DS11646 Rev 4

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SPC58EEx, SPC58NEx

Electrical characteristics

128

3.18.5

PSI5 timing

The following table describes the PSI5 timing.

3.18.6

CAN timing

The following table describes the CAN timing.

uCCLogic_0

CC D Threshold for detecting logic low

dCCRxD01

CC D

Sum of delay from actual input to the D input of the

first FF, rising edge

—10

dCCRxD10

CC D

Sum of delay from actual input to the D input of the

first FF, falling edge

—10

dCCRxAsymAccept15

CC D

Acceptance of asymmetry at receiving CC with

15 pF load

–31.5

dCCRxAsymAccept25

CC D

Acceptance of asymmetry at receiving CC with

25 pF load

–30.5

Table 70. RxD input characteristics (continued)

Symbol

Characteristic

Value

Unit

Min

Max

Table 71. PSI5 timing

Symbol

Parameter

Value

Unit

Min

Max

tMSG_DLY

CC D

Delay from last bit of frame (CRC0) to

assertion of new message received interrupt

—3

µs

tSYNC_DLY CC D

Delay from internal sync pulse to sync pulse

trigger at the SDOUT_PSI5_n pin

—2

µs

tMSG_JIT

CC D

Delay jitter from last bit of frame (CRC0) to

assertion of new message received interrupt

—

cycles(1)

tSYNC_JIT

CC D

Delay jitter from internal sync pulse to sync

pulse trigger at the SDOUT_PSI5_n pin

—

+/-±(1 PSI5_1µs_CLK +

1 PBRIDGEn_CLK)

cycles

1. Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.

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