FS5502 datasheet(53/113 Pages) NXP

53 / 113 page

NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

14.2 Application schematic

SLOPE

COMPENSATION

PWM

Lpi

Cpi2

Cpi1

1 nF

Cbat

VSUP1

VBAT

VSUP2

aaa-033263

current

sensing

gmEA

DRIVER

PRE_GHS

PRE_BOOT

PRE_SW

PRE_GLS

PRE_COMP

PRE_CSP

PRE_FB

Vref

single

package

VPRE

COUT_PRE

RSHUNT

LVPRE

CBOOT

RCOMP CCOMP

CHF

CONTROLLER

VPRE

Figure 8. VPRE schematic

A PI filter, with FRES = 1 / [2π x √(LCpi1)] and calculated for Fres < FPRE_SW / 10, is

required to filter VPRE switching frequency on the Battery line. VSUP1,2 pins must

be connected before the PI filter for a clean biasing of the device. Cpi1 capacitor shall

be implemented close to VSUP1,2 pins. Cpi2 capacitor shall be implemented close

to Q1. The bootstrap capacitor value should be sized to be >10 times the gate source

capacitor of Q1. Gate to source resistor on Q1 and Q2 is recommended in case of pin

disconnection to guarantee a passive switch OFF of the transistors.

14.3 Compensation network and stability

The external compensation network, made with RCOMP, CCOMP and CHF shall be

calculated for best compromise between stability and transient response, based on below

conceptual plot of Type 2 compensation network transfer function.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

53 / 113

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