AD9986 datasheet(6/37 Pages) AD

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Data Sheet

AD9986

SPECIFICATIONS

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Rev. 0 | 6 of 37

ADC DC SPECIFICATIONS

ADC setup in 6 GSPS, full bandwidth mode (all digital downconverters bypassed). For the minimum and maximum values, TJ = −40°C to

+120°C, and for the typical values, TA = 25°C, which corresponds to TJ = 80°C, unless otherwise noted.

Table 4. ADC DC Specifications

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC RESOLUTION

Bit

ADC ACCURACY

No Missing Codes

Guaranteed

Offset Error

0.04

%FSR

Offset Matching

0.03

%FSR

Gain Error

1.5

%FSR

Gain Matching

0.6

%FSR

DNL

0.32

LSB

INL

1.38

LSB

ADC ANALOG INPUTS

ADCxP and ADCxN

Differential Input Voltage

1.475

V p-p

Full-Scale Sine Wave Input Power

Input power level resulting in 0 dBFS tone level on fast Fourier

transform (FFT)

3.9

dBm

Common-Mode Input Voltage (VCMIN)

AC-coupled, equal to voltage at VCMx for ADCx input

Differential Input Resistance

100

Ω

Differential Input Capacitance

0.4

Return Loss

2.7 GHz

−4.3

2.7 GHz to 3.8 GHz

−3.6

3.8 GHz to 5.4 GHz

−2.9

CLOCK INPUT AND PHASE-LOCKED LOOP (PLL) FREQUENCY SPECIFICATIONS

For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply, unless otherwise noted.

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK INPUTS (CLKINP, CLKINN) FREQUENCY RANGES

12000

MHz

PHASE FREQUENCY DETECTOR (PFD) INPUT FREQUENCY RANGES

750

MHz

FREQUENCY RANGES ACCORDING TO CLOCK PATH CONFIGURATION

Direct Clock (PLL Off)

29001

12000

MHz

PLL Reference Clock (PLL On)

M divider set to divide by 1

750

MHz

M divider set to divide by 2

1500

MHz

M divider set to divide by 3

2250

MHz

M divider set to divide by 4

100

3000

MHz

PLL VOLTAGE CONTROLLED OSCILLATOR (VCO) FREQUENCY RANGES

VCO Output

Divide by 1

D divider set to divide by 1

5.8

GHz

Divide by 2

D divider set to divide by 2

2.9

GHz

Divide by 3

D divider set to divide by 3

1.93333

GHz

Divide by 4

D divider set to divide by 4

1.45

GHz

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