AD9986 datasheet(7/37 Pages) AD

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Data Sheet

AD9986

SPECIFICATIONS

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Rev. 0 | 7 of 37

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CLOCK OUTPUTS (ADC CLOCK DRIVER)

ADCDRVP and ADCDRVN

Differential Output Voltage Magnitude2

1.5 GHz

740

mV p-p

2.0 GHz

690

mV p-p

3 GHz

640

mV p-p

6 GHz

490

mV p-p

Differential Output Resistance

100

Common-Mode Voltage

AC-coupled

0.5

1 The minimum direct clock frequency is limited by the minimum DAC (core) sample rate, as specified in Table 6. The clock receiver can accommodate the full range

between the minimum PLL reference clock frequency and the maximum direct clock frequency.

2 Measured with differential 100 Ω load and less than 2 mm of printed circuit board (PCB) trace from package ball.

DAC AND ADC SAMPLE RATE SPECIFICATIONS

Nominal supplies. For the minimum and maximum values, TJ = −40°C to +120°C and ±5% of nominal supply. For the typical values, TA = 25°C,

which corresponds to TJ = 80°C, unless otherwise noted.

Table 6. DAC Sample Rate Specifications

Parameter

Min

Typ

Max

Unit

DAC SAMPLE RATE1

Minimum

2.9

GSPS

Maximum

GSPS

1 Pertains to the update rate of the DAC core, independent of datapath and JESD204 mode configuration.

Table 7. ADC Sample Rate Specifications

Parameter

Min

Typ

Max

Unit

ADC SAMPLE RATE1

Minimum

1.45

GSPS

Maximum

GSPS

Aperture Jitter2

fs rms

1 Pertains to the update rate of the ADC core, independent of datapath and JESD204 mode configuration.

2 Measured using a signal-to-noise ratio (SNR) degradation method with the DAC disabled, clock divider = 1, fADC = 4 GSPS, and input frequency (fIN) = 5.55 GHz.

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