ADPA7008AEHZ-R7 datasheet(22/28 Pages) AD

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Data Sheet

ADPA7008

BIASING THE ADPA7008 WITH THE LOW NOISE LTM8063

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Rev. 0 | 22 of 28

Figure 72. A Complete Gate and Drain Voltage Biasing Circuit for the ADPA7008

As shown in Figure 72, the drain voltage is generated by the

LTM8063. The negative gate voltage is generated by the ADP5600.

The exact gate voltage is set by a resistor divider between the

LDO_OUT and FB pins on the ADP5600. The equation for setting

the gate voltage is VGG1 = −0.5(1 + R1/(R2 + R3)), where R2

is a potentiometer. To achieve a drain voltage of 1500 mA, the

recommended value for VGG1 is −0.63 V. To set this voltage, R1

and R3 were set to 22.1 kΩ and 11.3 kΩ, respectively, and the R2

potentiometer was set to 100 kΩ, which allows VGG1 to swing from

approximately −1.5 V to −0.6 V. To ensure that the gate voltage

is active before the drain voltage, the PGOOD signal from the

ADP5600 is used to gate all devices in the drain voltage generation

path. The ADP5600 PGOOD output signal is scaled using a resistor

divider such that the LTM8063 drain voltage generator turns on

after the ADP5600 output does. Figure 73 shows the turn on

sequence and turn off sequence. Notice how VDD turns on a few

milliseconds after VGG. This sequencing is controlled by the scaled

PGOOD signal.

Figure 73. Turn On Sequence and Turn Off Sequence

ADPA7008AEHZ-R7 데이터시트(PDF) 22 Page - Analog Devices