ATAR080 datasheet(27/68 Pages) ATMEL

27 / 68 page

ATAR080

4675D–4BMCU–12/04

Universal Timer/Counter/

Communication Module

(UTCM)

The Universal Timer/Counter/Communication Module (UTCM) consists of Timer 1,

Timer 2 and a Synchronous Serial Interface (SSI).

•

Timer 1 is an interval timer that can be used to generate periodical interrupts and as

prescaler for Timer 2, the serial interface and the watchdog function.

•

Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).

•

The SSI operates as a two-wire serial interface or as a shift register for modulation.

The modulator units work together with the timers and shift the data bits out of the

shift register.

There is a multitude of modes in which the timers and the serial interface can work

together.

Figure 26. UTCM Block Diagram

Timer 1

Timer 1 is an interval timer which can be used to generate periodic interrupts and as a

prescaler for Timer 2, Timer 3, the serial interface and the watchdog function.

Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or

SYSCL. The timer output signal can be used as a prescaler clock or as SUBCL and as a

source for the Timer 1 interrupt. Because of other system requirements, Timer 1 output

T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU

core

→sleep and OSC-Stop →yes) the output T1OUT is stopped (T1OUT = 0). Never-

theless, Timer 1 can be active in SLEEP and generate Timer 1 interrupts. The interrupt

is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the

T1C2 register. The time interval for the timer output can be programmed via the Timer 1

control register T1C1.

This timer starts running automatically after any power-on reset! If the watchdog func-

tion is not activated, the timer can be restarted by writing into the T1C1 register with

T1RM = 1.

MUX

Watchdog

Interval/Prescaler

Timer 1

Modu-

lator 2

4-bit Counter 2/1

Compare 2/1

MUX

DCG

8-bit Counter 2/2

Compare 2/2

Control

Timer 2

MUX

8-bit Shift-register

Receive-buffer

Transmit-buffer

Control

SSI

SCL

INT4

INT2

NRST

INT3

POUT

TOG2

T1OUT

SUBCL

SYSCL

from clock module

T2I

T2O

I/O bus

ATAR080 데이터시트(PDF) 27 Page - ATMEL Corporation

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