PCA2117DUGSSLASHDA datasheet(64/107 Pages) NXP

64 / 107 page

PCA2117

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Product data sheet

Rev. 4 — 8 April 2015

64 of 107

NXP Semiconductors

PCA2117

Automotive LCD driver for character displays

Bus interfaces

9.1 Control byte and register selection

After initiating the communication over the bus and sending the slave address (I2C-bus,

see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The

purpose of this byte is to indicate both, the content for the following data bytes (RAM or

command) and to indicate that more control bytes will follow.

Typical sequences could be:

• Slave address/subaddress - control byte - command byte - control byte - command

byte - control byte - command byte - end

• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end

• Slave address/subaddress - control byte - command byte - control byte - RAM byte -

end

This allows sending a mixture of RAM and command data in one access or alternatively,

to send just one type of data in one access. In this way, it is possible to configure the

device and then fill the display RAM with little overhead. The display bytes are stored in

the display RAM at the address specified by the data pointer.

9.2 I2C interface

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

In Chip-On-Glass (COG) applications, where the track resistance between the SDA

output pin to the system SDA input line can be significant, the bus pull-up resistor and the

Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a

Table 40.

Control byte description

Bit

Symbol

Value

Description

7CO

continue bit

last control byte

control bytes continue

6 to 5

RS[1:0]

00, 10, 11

command register

RAM data

4 to 0

unused

Fig 44. Control byte format

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