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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCA2117DUGS/DA 데이터시트(PDF) 87 Page - NXP Semiconductors |
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PCA2117DUGS/DA 데이터시트(HTML) 87 Page - NXP Semiconductors |
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87 / 107 page  PCA2117 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 4 — 8 April 2015 87 of 107 NXP Semiconductors PCA2117 Automotive LCD driver for character displays 14.3 SPI-bus timing characteristics [1] No load value; bus is held up by bus capacitance; use RC time constant with application values. Table 53. SPI-bus characteristics VDD1, VDD2 = 2.5 V to 5.5 V; VSS1 = 0 V; VLCD = 4.0 V to 16.0 V; Tamb = 40 C to +105 C; unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS1 to VDD1 (see Figure 60). Symbol Parameter Conditions Min Max Unit Pin SCL fclk(SCL) SCL clock frequency - 3.0 MHz tSCL SCL time 333 - ns tclk(H) clock HIGH time 100 - ns tclk(L) clock LOW time 150 - ns tr rise time for SCL signal - 100 ns tf fall time for SCL signal - 100 ns Pin CE tsu(CE_N) CE_N set-up time 30 - ns th(CE_N) CE_N hold time 30 - ns trec(CE_N) CE_N recovery time 30 - ns Pin SDI tsu set-up time set-up time for SDI data 30 - ns th hold time hold time for SDI data 30 - ns Pin SDO td(R)SDO SDO read delay time CL = 100 pF - 150 ns tdis(SDO) SDO disable time [1] -50 ns tt(SDI-SDO) transition time from SDI to SDO to avoid bus conflict 0 - ns |
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