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WM8940CGEFL/V 데이터시트(PDF) 52 Page - Cirrus Logic

부품명 WM8940CGEFL/V
상세설명  Mono CODEC with Speaker Driver
PDF  88 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8940CGEFL/V 데이터시트(HTML) 52 Page - Cirrus Logic

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WM8940
52
Rev 4.4
LEFT
PHASE
RIGHT
PHASE
FRAME
BCLK
DACDAT /
ADCDAT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
Figure 26 Right Justified Audio Interface (assuming n-bit word length)
In I2S mode, the MSB is available on the second rising edge of BCLK following a FRAME transition.
The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK
frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and
the MSB of the next.
LEFT
PHASE
RIGHT
PHASE
FRAME
BCLK
DACDAT
/ADCDAT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
Figure 27 I2S Audio Interface (assuming n-bit word length)
In DSP/PCM mode, the left channel MSB is available on either the 1st (Mode B) the 2nd (Mode A)
rising edge of BCLK (selectable by FRAMEP) following a rising edge of FRAME. Right channel data
immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,
there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
FRAMEP should be set to 0 in this mode.
FRAME
BCLK
DACDAT /
ADCDAT
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
Input Word Length (WL)
1/fs
Figure 28 DSP/PCM Mode Audio Interface (Mode A, FRAMEP=0)



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