AT24C01C datasheet(19/45 Pages) MICROCHIP

19 / 45 page

Figure 7-2. Page Write

SCL

SDA

Start

Master

ACK

from

Slave

ACK

from

Slave

Device Address Byte

Word Address Byte

MSB

ACK

from

Slave

Stop

Master

ACK

from

Slave

Data Word (n)

Data Word (n+x), max of 8 without rollover

MSB

A6 A5

D7 D6

D3 D2 D1

D7 D6

D3 D2 D1

7.3

Acknowledge Polling

An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would

prefer not to wait the fixed maximum write cycle time (tWR). This method allows the application to know

immediately when the Serial EEPROM write cycle has completed, so a subsequent operation can be

started.

Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated.

This involves repeatedly sending a Start condition followed by a valid device address byte with the R/W

bit set at logic ‘0’. The device will not respond with an ACK while the write cycle is ongoing. Once the

internal write cycle has completed, the EEPROM will respond with an ACK, allowing a new read or write

operation to be immediately initiated. A flowchart has been included below in Figure 7-3 to better illustrate

this technique.

Figure 7-3. Acknowledge Polling Flowchart

Did

the device

ACK?

Send any

Write

protocol.

Send

Stop

condition

to initiate the

Write cycle.

Send Start

condition followed

by a valid

Device Address

byte with R/W = 0.

Proceed to

next Read or

Write operation.

YES

7.4

Write Cycle Timing

The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that

begins the internal write cycle to the Start condition of the first device address byte sent to the

AT24C01C/AT24C02C that it subsequently responds to with an ACK. Figure 7-4 has been included to

AT24C01C/AT24C02C

Write Operations

Datasheet

DS20006111A-page 19

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