HT46R71D datasheet(21/46 Pages) HOLTEK

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HT46R71D

Rev. 1.00

January 9, 2006

REGCEN

CHPEN

Charge

Pump

VOCHP

Regulator

VOREG Pin

OPA ADC

Description

OFF

VDD

OFF

Hi-Impedance

Disable

The whole module is disable,

OPA/ADC will lose the Power

OFF

VDD

3.3V

Active

Use for VDD is greater than 3.6V

(VDD>3.6V)

´VDD

3.3V

Active

Use for VDD is less than 3.6V

(VDD=2.2V~3.6V)

The CHPCKD4~0 bits are use to set the clock divider to

generate the desired clock frequency to provide the

charge pump working. The actual frequency is decide

by the following formula.

The Actual Charge Pump Clock= (f SYS/16)/

(CHPCKD+1).

The suggestion clock frequency of the charge pump is

20kHz. Application need to set the correct value to get

the desired clock frequency. e.g. for the 4MHz applica-

tion, the CHPCKD should be set to 12, and for 2MHz ap-

plication, the correct CHPCKD is 6.

The REGCEN bit in the CHPRC is the Regulator/

Charge-pump module enable/disable control bit. If this

bit is disabled, then the regulator will be disabled and the

charge pump will be also be disabled to save power.

When REGCEN = 0, the module will enter a Power

Down Mode ignoring the CHPEN setting. The ADC and

OPA will also be disabled to reduce power.

If REGCEN is set to logic

²1², the regulator will be en-

abled. If CHPEN is enabled, the charge pump will be ac-

tive and will use VDD as its input to generate the double

voltage output. This double voltage will be used as the

input of the regulator. If CHPEN is set to logic

²0², the

charge pump is disabled and the charge pump output

will be equal to the charge pump input (VDD).

Users need to take care of the VDD voltage, if the voltage

is under 3.6V, then CHPEN should be set to 1 to enable

the charge pump, otherwise CHPEN should be set to

zero. If the Charge pump is disabled and VDD is under

3.6V then the output voltage of the regulator will not be

guaranteed.

ADC

- Dual Slope

A Dual Slope A/D converter is implemented in this

microcontroller. The dual slope module includes an Op-

erational Amplifier and a buffer for the amplification of

differential signals, an Integrator and a comparator for

the main dual slope AD converter.

In addition, there is also an integrated band gap voltage

generator for the 1.5V low temperature sensitive refer-

ence voltage. This reference voltage is used as the zero

adjustment and for a single end type reference voltage.

There are 2 special function registers related to this

block including: ADCR and ADCD. The ADCR register

is the A/D control register, which controls the ADC block

power on/off, the chopper clock on/off, the charge/dis-

charge control and is also used to read out the compara-

tor output status. The ADCD is the A/D Chopper clock

divider register, which define the chopper clock to the

ADC module.

A m p l i f i e r

D O P A P

D O P A N

O n C h i p

O f f C h i p

B u f f e r

D O P A O D C H O P

D S R R

D S R C

I n t e g r a t o r

D S C C

C o m p a r a t o r

P W R

C o n t r o l

A D C M P O

A D P W R E N

V O R E G

A D D I S C H 0

A D D I S C H 1

V D S O

V I N T

R v f 1

R v f 2

V C M P

Note: VINT,VCMP signal can come from different R groups which are selected by software registers.

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