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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SH79F6489P/080PR 데이터시트(PDF) 87 Page - SINOWEALTH Electronic Ltd |
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SH79F6489P/080PR 데이터시트(HTML) 87 Page - SINOWEALTH Electronic Ltd |
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87 / 152 page  SH79F6488/SH79F6489 87 8.3.9 Registers Table 8.10 Serial Peripheral Control Register A4H Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPCON DIR MSTR CPHA CPOL SSDIS SPR2 SPR1 SPR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Value (POR/WDT/LVR/PIN) 0 0 0 0 0 0 0 0 Bit Number Bit Mnemonic Description 7 DIR Transfer Direction Selection 0: MSB first 1: LSB first 6 MSTR Serial Peripheral Master 0: Configure the SPI as a Slave 1: Configure the SPI as a Master 5 CPHA Clock Phase 0: Data sampled on first edge of SCK period 1: Data sampled on second edge of SCK period 4 CPOL Clock Polarity 0: SCK line low in idle state 1: SCK line high in idle state 3 SSDIS SS ——— Disable 0: Enable SS ——— pin in both Master and Slave modes 1: Disable SS ——— pin in both master and slave modes MODF interrupt request will not generate, if SSDIS is set. In Slave mode, this bit has no effect if CPHA = 0. 2-0 SPR[2:0] Serial Peripheral Clock Rate 000: fSYS/4 001: fSYS/8 010: fSYS/16 011: fSYS/32 100: fSYS/64 Others: fSYS/128 |
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