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SH79F6489P/080PR 데이터시트(PDF) 125 Page - SINOWEALTH Electronic Ltd |
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SH79F6489P/080PR 데이터시트(HTML) 125 Page - SINOWEALTH Electronic Ltd |
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125 / 152 page ![]() SH79F6488/SH79F6489 125 8.11 Watchdog Timer (WDT) and Reset State 8.11.1 Features Auto detect Program Counter(PC) over range, and generate OVL Reset WDT runs even in the Power-Down mode Selectable different WDT overflow frequency OVL Reset To enhance the anti-noise ability, SH79F6488/SH79F6489 built in Program Counter (PC) over range detect circuit, if program counter value is larger than flash romsize, or detect operation code equal to A5H which is not exist in 8051 instruction set, a OVL reset will be generate to reset CPU, and set WDOF bit. So, to make use of this feature, you should fill unused flash rom with A5H. Watchdog Timer The watchdog timer is a down counter, and its clock source is an independent built-in RC oscillator, so it always runs even in the Power-Down mode. The watchdog timer will generate a device reset when it overflows. It can be enabled or disabled permanently by the code option. The watchdog timer control bits (WDT.2-0) are used to select different overflow frequency. The watchdog timer overflow flag (WDOF) will be automatically set to “1” by hardware when overflow happens. To prevent overflow happen, by reading or writing the WDT register RSTSTAT, the watchdog timer should re-count before the overflow happens. Note: After base timer or LCD on, if WDT is on ,WDT cannot be turn off in Power-Down mode. Therefore, users need to read or write RSTSTAT register in case to WDT overflow. |
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