L9908 datasheet(68/153 Pages) STMICROELECTRONICS

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DTP_CFG2

DTP_CFG1

DTP_CFG0

Description

0.35 μs

0.5 μs

1 μs – Default

1.5 μs

2 μs

4 μs

Table 62. Dead Time Protection accuracy

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

DTP_tflt_acc

Dead Time Filter accuracy

CLK_SSM_EN = 0

-15

Note:

All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise

specified. Where not specified the parametrical operating range equals the functional operating range.

5.12.3

Shoot-Through Protection (STP)

Independently of the activation of DTP, L9908 implements a monitoring unit to detect the dangerous condition

when HS and LS of the same half bridge are driven on at the same time. The diagnosis is performed at two

levels: on the devices PWM inputs from uC (INHn/INLn) and on the Ext. FET Vgs; this allows a diagnosis

coverage both on external and internal shoot-through faults.

The first diagnosis level consists in a dedicated digital counter for each half bridge PWM inputs (INHn/INLn

couple) set/reset by the logic AND between INHn and INLn and integrates the time interval where the INHn and

the INLn are high together.

If INHn=INLn=’1’ occurs for an interval longer than T_stp_pwm_flt the flag STP_PWM_n is set. The error flag

remains set until the failure condition is removed and the flag is cleared by the SPI command.

In addition to STP, an interlocking protection function on INHn and INLn is implemented: when the main logic

processes a rising edge event on INHn/INLn a masking on the opposite signal (INLn/INHn respectively) is applied

for the entire duration of the INHn/INLn on pulse. During this interval any rising edge on the opposite signal is

ignored. In case INHn/INLn rising edge is synchronous then INLn has the priority.

The interlocking protection is always active and cannot be disabled.

Figure 41. Interlocking protection on PWM inputs: functional operation

L9908

Half bridges gate drivers

DS13546 - Rev 3

page 68/153

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