전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

L99H02 데이터시트(PDF) 21 Page - STMicroelectronics

부품명 L99H02
상세설명  H-bridge gate driver for automotive applications
PDF  51 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99H02 데이터시트(HTML) 21 Page - STMicroelectronics

Back Button L99H02 Datasheet HTML 17Page - STMicroelectronics L99H02 Datasheet HTML 18Page - STMicroelectronics L99H02 Datasheet HTML 19Page - STMicroelectronics L99H02 Datasheet HTML 20Page - STMicroelectronics L99H02 Datasheet HTML 21Page - STMicroelectronics L99H02 Datasheet HTML 22Page - STMicroelectronics L99H02 Datasheet HTML 23Page - STMicroelectronics L99H02 Datasheet HTML 24Page - STMicroelectronics L99H02 Datasheet HTML 25Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 51 page
background image
DS12547 Rev 6
21/51
L99H02
Electrical specifications
50
2.5
SPI - electrical characteristics
VS = 6 V to 28 V, VCC = 3 V to 5.3 V, Tj = -40°C to 150°C, unless otherwise specified. The
voltages are referred to GND and currents are assumed positive, when the current flows
into the pin.
DI timing parameters tested in production by a passed/failed test:
Tj = -40°C / +25°C: SPI communication @ 2 MHz.
Tj = +125°C: SPI communication @ 1.25 MHz.
Table 19. DI timing
Item
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
19.1
tCLK
Clock period
1000
ns
19.2
tCLKH
Clock high time
400
ns
19.3
tCLKL
Clock low time
400
ns
19.4
tset CSN
CSN setup time, CSN low
before rising edge of CLK
400
ns
19.5
tset CLK
CLK setup time, CLK high
before rising edge of CSN
400
ns
19.6
tset DI
DI setup time
200
ns
19.7
thold DI
DI hold time
200
ns
19.8
tr in
Rise time of input signal DI,
CLK, CSN
100
ns
19.9
tf in
Fall time of input signal DI,
CLK, CSN
100
ns
Table 20. DO
Item Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
20.1
VDOL
Low-level output
voltage
ID =-4 mA
0.2
0.4
V
20.2
VDOH
High-level output
voltage
ID =4 mA
VCC -0.4 VCC -0.2
V
20.3
IDOLK
Tristate leakage
current
VCSN =VCC;
0V< VDO <VCC
-10
10
µA
20.4
CDO(1)
1.
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Tristate input
capacitance
VCSN =VCC;
0V< VCC <5.3 V
10
15
pF



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com