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L99H02 데이터시트(PDF) 35 Page - STMicroelectronics |
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L99H02 데이터시트(HTML) 35 Page - STMicroelectronics |
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35 / 51 page ![]() DS12547 Rev 6 35/51 L99H02 Functional description of the SPI 50 4.4.1 SPI clock monitor and watchdog Figure 11. Global error flag diagram Note: Writing a “1” to RWD - bit in ApplRegx restarts the internal watchdog counter. The clock monitor counts the number of clock pulses during a communication frame (while CSN is low). If the number of SCK pulses does not correspond with the frame width indicated in the <SPI-frame-ID> (ROM address 03hex) the frame is ignored and the bit <frame error> in the <Global Status Byte> is set. Note: Due to this safety functionality, daisy chaining the SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. SCK SDI SDO / Err CSN Communication Error WD counter Watchdog Failure Global Status Byte Global Error Flag Clock- Monitor RWD ApplRegx bit 7 GAPGCFT00670 |
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