STA8100GA datasheet(14/42 Pages) STMICROELECTRONICS

14 / 42 page

General description

STA8100GA

14/42

DS13006 Rev 4

3.4.4

AXI bus

AXI Bus matrix handles major high bandwidth transactions for STA8100GA. It connects the

SRAM, boot ROM and external memory controllers, which provide access to the external

Flash. ARM® acts as a master on this bus with the highest priority.

3.5

APB peripherals

3.5.1

APB bridge 2 peripherals

AHB to APB Bridge 2 sits on AHB bus matrix 0 as a slave and is used to connect

peripherals. These slaves will be accessed by AHB masters connected to AHB bus

matrix 0.

The peripherals connected to APB 2 are:

UART2, MSP1, GPIO PORT 2, MTU1.

3.5.2

APB bridge 1 peripherals

AHB to APB bridge 1 sits on AHB bus matrix 0 as a slave and is used to connect

peripherals. These slaves will be accessed by AHB masters connected to AHB bus matrix0.

The peripherals connected to APB 1 are UART1, EFT0, EFT1, GPIO PORT 0 and 1, MTU0,

OTP, SSP, Thermal sensor, Watchdog timer.

3.5.3

APB bridge 0 peripherals

AHB to APB bridge 0 sits on AHB bus matrix 0 as a slave and is used to connect

peripherals. These slaves will be accessed by AHB masters connected to AHB bus matrix0.

The peripherals connected to APB 0 are the ones on the always on domain:

PRCC always ON, RTC.

3.5.4

AHB slave devices

There are some AHB slave devices which are connected to AHB bus matrix 0.

3.6

eSRAM

256 KB of embedded RAM are available on top of the TCM RAM.

The eSRAM is directly connected to the MCU through the AXI bus. It can be used for data

and instruction.

3.7

Serial Flash Memory Controller (SFC)

The Serial Flash Memory Controller supports single, quad and octal memories. It can be

used for in place execution thanks to direct memory mapping.

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