STA8100GA datasheet(20/42 Pages) STMICROELECTRONICS

20 / 42 page

General description

STA8100GA

20/42

DS13006 Rev 4

3.19

Reset

After a reset, the Cortex® M7 is woken-up by the ROM code.

The PRCC module is used to sequence through all the steps needed to properly reset the

device and prepare it to fetch the first instruction of the user application code.

STA8100GA has the following reset options:

Pad reset: SoC will have active low chip reset (RESET) pad. Low (zero) status on this

pad will keep device in the reset. Assertion of this pin low should be minimum of 5 ms.

Power on reset: The power on reset circuitry is embedded in the main voltage regulator

built on HV supply (VCORE_IN) of regulator. It ensures all voltage monitors are under

reset state until VCORE_IN (or VDD_EXT_REG) minimum voltage is reached.

Hardware resets: The internal voltage regulator embeds multiple LVD (Low Voltage

Detector) and HVD (High Voltage Detector) which are used in the reset sequence.

Soft reset: Different peripherals present on STA8100GA can be reset independently

through registers present inside PRCC module.

3.20

Power Management Unit (PMU)

STA8100GA embeds five voltage regulators (LDO):

Table 11. Boot peripheral selection

ROM action

UART2-TX = 0

Boot from flash memory - SFC controller

UART2-TX = 1

Boot from peripheral - UART

Table 12. LDO on-chip regulators

LDO

Supply regions

Input voltage

Typical output voltage

at 25°C

CORE LDO

Core

VCORE_IN = 1.62 – 3.6 V

1.2 V

LDO2v5

Safmem, temp sensor VIO_IN = 3.3 V

2.5 V

IO LDO

IO ring 1

VIO_IN = 3.3 V

1.8 V

BACKUP LDO

Always on

VBK_IN = 1.62 – 3.6 V

1.2 V

RFLDO

VRF_IN = 1.62 – 3.6 V

1.1 V

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