L9788 datasheet(159/264 Pages) STMICROELECTRONICS

159 / 264 page

DS12308 Rev 4

159/264

L9788

CAN FD interface

263

Table 73. CAN Receiver input characteristics during low power mode, biasing inactive

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

VTHdomLP

Differential receiver

threshold voltage recessive

to dominant state

-12 V ≤ VCANH ≤ +12 V,

-12 V ≤ VCANL ≤ +12 V

(0.5)

1.05

VTHrecLP

Differential receiver

threshold voltage dominant

to recessive state

-12 V ≤ VCANH ≤ +12 V,

-12 V ≤ VCANL ≤ +12 V

0.4

(0.9)

Table 74. CAN Receiver input resistance

Symbol

Parameter

Test condition

Min

Typ

Max

Unit

Rdiff

Differential internal

resistance

VTXDC = VTXDCHiGH; No Load

100

kΩ

RCANH,

CANL

Single Ended

Internal resistance

VTXDC = VTXDCHiGH; No Load

kΩ

Internal Resistance

matching

RCANH,CANL

Biasing active;

VTXDC=VTXDCHIGH; no load

R = 2 x (RCAN_H - RCAN_L) /

(RCAN_H + RCAN_L)

-0.03

0.03

Cin

Internal capacitance Guaranteed by design

Cin, diff

Differential internal

capacitance

Guaranteed by design

Table 75. CAN transceiver delay

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

tLOOP,hl

Loop delay TXDC to

RXDC (High to Low)

RL = 60 Ω (±1%); C2 = 100pF (±1%);

30% VTXDC – 30% VRXDC;



TXDC fall time = 10ns (90% - 10%);

CRX = 15 pF

255

tLOOP,lh

Loop delay TXDC to

RXDC (Low to High)

RL = 60 Ω (±1%); C2 = 100pF (±1%);

70% VTXD – 70% VRXD;



TXDC fall time = 10ns (10% - 90%);

CRX = 15 pF

255

TBit(RXD)

≤ 1 Mb/s

Recessive bit symmetry

at RXDC

RL = 60 Ω (±1%); VDIFF: 0.5 V(falling) -

0.9 V(rising); C2 = 100pF (±1%);

CRX = 15 pF; TXD rise and fall time =

10 ns (10% - 90%, 90% - 10%);



Test signal to be applied on the TXD

input of the implementation is a square

wave signal with a positive duty cycle of

1/6 and a period of six times the

nominal recessive bit width.

Rectangular pulse signal TTXDC=

6000ns, high pulse 1000ns, low pulse

5000ns

745

1000 1255

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