L9788 datasheet(35/264 Pages) STMICROELECTRONICS

35 / 264 page

DS12308 Rev 4

35/264

L9788

Operation behavior

263

Figure 7. Wake up timer block diagram

WAKE_UP_TIMER_CNT Register can be read via MSC. Wake up timer_SET Register can

be read and write via MSC.

3.1.8

Power on with PHOLD_EN (EOT function 3)

The chip is kept switched on by an MSC command (PHOLD_EN CONFIG_REG1[0]) even

though one of the power down sources has been asserted (KEY_IN, WK_IN,

WAKE_UP_TIMER, WAKE_UP_CAN). The chip is kept on in power hold mode for a time

programmed (default is infinity) by MSC (PHOLD_TIME[0:1] CONFIG_REG1 (D1;D2)). This

is also EOT function 3. The power hold mode is enabled by MSC and is cleared by the

conditions reported in the reset matrix.

After setting the PHOLD_EN=CONFIG_REG1[0]=1 the PHOLD and the PHOLD timer are

enabled when the KEY_DET, WK_IN_DET, WAKE_UP_EOT_DET, WAKE_UP_CAN_DET

detections are not active. The PHOLD_TIMER[14:0]=READ12.FRAME[2:1] starts counting

when the KEY_DET, WK_IN_DET, WAKE_UP_EOT_DET, WAKE_UP_CAN_DET

detections are cleared. When the PHOLD_TIME=CONFIG_REG1[2:1] is configured as 00

(default) the timeout is disabled and the PHOLD_TIMER[14:0]=READ12.FRAME[2:1] is

read always at 0.

Table 12. Wake up timer resolution

range

resolution

0 - 16777215

1 second

V3V3 regulator

Oscillator

32KHz

internal

Wake Up Timer Register

(read only)

Wake Up SET Timer Register

(read and write)

comparator

MSC Register in VB block

Main Relay Driver

MSC Register in STBY block

STBY block

VB block

STBY

GADG2411161451PS

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