STA350B datasheet(55/94 Pages) STMICROELECTRONICS

55 / 94 page

DocID018572 Rev 7

55/94

STA350B, STA350BW

to power down the power-stage, then the master clock to all internal hardware except the

I2C block is gated. This places the IC in a very low power consumption state.

8.6.7

External amplifier power-down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed in a low-power state (disabled). This

8.7

Volume control registers (addr 0x06 - 0x0A)

8.7.1

Mute/line output configuration register

Line output is active when OCFG = 00 only. In this case LOC determines the line output

configuration. The source of the line output is always the channel 1 and 2 inputs.

8.7.2

Master volume register

8.7.3

Channel 1 volume

Table 50. External amplifier power-down

Bit

R/W

RST

Name

Description

R/W

EAPD

0: External power stage power down active

1: Normal operation

LOC1

LOC0

Reserved

C3M

C2M

C1M

MMUTE

0000

Table 51. Line output configuration

LOC[1:0]

Line output configuration

Line output fixed - no volume, no EQ

Line output variable - CH3 volume effects line output, no EQ

Line output variable with EQ - CH3 volume effects line output

MV7MV6

MV5MV4

MV3

MV2

MV1MV0

1111

C1V7

C1V6

C1V5

C1V4

C1V3

C1V2

C1V1

C1V0

0110

0000

STA350B 데이터시트(PDF) 55 Page - STMicroelectronics

STA350B 데이터시트(HTML) 55 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

데이터시트 다운로드

링크 URL