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CS47L35 데이터시트(PDF) 52 Page - Cirrus Logic

부품명 CS47L35
상세설명  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 데이터시트(HTML) 52 Page - Cirrus Logic

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DS1085F3
CS47L35
4.3 Digital Core
The following description of the DRC is applicable to each of the DRCs. The associated control fields are described in
Table 4-13 and Table 4-14 for DRC1 and DRC2.
4.3.5.1 DRC Compression, Expansion, and Limiting
The DRC supports two different compression regions, separated by a knee at a specific input amplitude. In the region
above the knee, the compression slope DRCn_HI_COMP applies; in the region below the knee, the compression slope
DRCn_LO_COMP applies. Note that n identifies the applicable DRC 1 or 2.
The DRC also supports a noise-gate region, where low-level input signals are heavily attenuated. This function can be
enabled or disabled according to the application requirements. The DRC response in this region is defined by the
expansion slope DRCn_NG_EXP.
For additional attenuation of signals in the noise-gate region, an additional knee can be defined (shown as Knee 2 in
Fig. 4-18). When this knee is enabled, this introduces an infinitely steep drop-off in the DRC response pattern between the
DRCn_LO_COMP and DRCn_NG_EXP regions.
The overall DRC compression characteristic in steady state (i.e., where the input amplitude is near constant) is shown in
Fig. 4-18.
Table 4-11. DRC Enable
Register Address
Bit
Label
Default
Description
R3712 (0x0E80)
DRC1_ctrl1
1
DRC1L_ENA
0
DRC1 (left) enable
0 = Disabled
1 = Enabled
0
DRC1R_ENA
0
DRC1 (right) enable
0 = Disabled
1 = Enabled
R3720 (0x0E88)
DRC2_ctrl1
1
DRC2L_ENA
0
DRC2 (left) enable
0 = Disabled
1 = Enabled
0
DRC2R_ENA
0
DRC2 (right) enable
0 = Disabled
1 = Enabled



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