CS47L35 datasheet(22/300 Pages) CIRRUS

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DS1085F3

CS47L35

3 Characteristics and Specifications

Table 3-20. Control Interface Timing—Four-Wire (SPI) Mode

The following timing information is valid across the full range of recommended operating conditions.

Parameter 1, 2

1.Control interface timing—SPI Mode (write

cycle)

2.Control interface timing—SPI Mode (read

cycle)

Symbol

Min

Typ

Max

Units

SS falling edge to SCLK rising edge

tSSU

2.6

—

SCLK falling edge to SS rising edge

tSHO

0—

—

SCLK pulse cycle time

SYSCLK disabled (SYSCLK_ENA = 0)

SYSCLK_ENA = 1, SYSCLK_FREQ = 000

SYSCLK_ENA = 1, SYSCLK_FREQ > 000

tSCY

50.0

76.8

38.4

—

SCLK pulse width low

tSCL

15.3

—

SCLK pulse width high

tSCH

15.3

—

MOSI to SCLK set-up time

tDSU

1.5

—

MOSI to SCLK hold time

tDHO

1.7

—

SCLK falling edge to MISO transition

SCLK slew (90%–10%) = 5 ns, CLOAD (MISO) = 25 pF

tDL

—

12.6

(input)

SCLK

(input)

MOSI

(input)

tSSU

tSCH

tSCL

tSCY

tDHO

tDSU

tSHO

SCLK

(input)

MISO

(output)

tDL

(input)

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