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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CS47L35 데이터시트(PDF) 70 Page - Cirrus Logic |
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CS47L35 데이터시트(HTML) 70 Page - Cirrus Logic |
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70 / 300 page  70 DS1085F3 CS47L35 4.3 Digital Core There are two isochronous sample-rate converters: ISRC1 and ISRC2. Each ISRC supports two-way, four-channel conversion paths between sample rates on the SYSCLK domain. The ISRCs are described in Section 4.3.14. The sample rate of different blocks within the CS47L35 digital core are controlled as shown in Fig. 4-26. The x_RATE fields select the applicable sample rate for each respective group of digital functions. The x_RATE fields must not be changed if any of the x_SRCn fields associated with the respective functions is nonzero. The associated x_SRCn fields must be cleared before writing new values to the x_RATE fields. A minimum delay of 125 s must be allowed between clearing the x_SRCn fields and writing to the associated x_RATE fields. See Table 4-21 for details. |
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