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CS47L35 데이터시트(PDF) 114 Page - Cirrus Logic

부품명 CS47L35
상세설명  Smart Codec with Low-Power Audio DSP
PDF  300 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L35 데이터시트(HTML) 114 Page - Cirrus Logic

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DS1085F3
CS47L35
4.7 Digital Audio Interface Control
Note: The CS47L35 is a 24-bit device. If the user operates the CS47L35 in 32-Bit Mode, the 8 LSBs are ignored on the
receiving side and not driven on the transmitting side. It is therefore recommended to add a pull-down resistor if
necessary to the RXDAT line and the TXDAT line in TDM mode.
4.7 Digital Audio Interface Control
This section describes the configuration of the CS47L35 digital audio interface paths.
AIF1 supports up to six input signal paths and up to six output signal paths; AIF2 and AIF3 support up to two channels of
input and output signal paths. The digital audio interfaces can be configured as master or slave interfaces; mixed master/
slave configurations are also possible.
Each input and output signal path can be independently enabled or disabled. The AIF output (TX) and AIF input (RX) paths
use shared BCLK and LRCLK control signals.
The digital audio interface supports flexible data formats, selectable word length, configurable time-slot allocations, and
TDM tristate control.
The audio interfaces can be reconfigured while enabled, including changes to the LRCLK frame length and the channel
time-slot configurations. Care is required to ensure that any on-the-fly reconfiguration does not cause corruption to the
active signal paths. Wherever possible, it is recommended to disable all channels before changing the AIF configuration.
4.7.1
AIF Sample-Rate Control
The AIF RX inputs may be selected as input to the digital mixers or signal-processing functions within the CS47L35 digital
core. The AIF TX outputs are derived from the respective output mixers.
The sample rate for each digital audio interface AIFn is configured using the respective AIFn_RATE field—see Table 4-21.
Note that sample-rate conversion is required when routing the AIF paths to any signal chain that is configured for a different
sample rate.
Figure 4-47. TDM with Processor as Master
TXDAT
LRCLK
RXDAT
BCLK
TXDAT
LRCLK
RXDAT
BCLK
Processor
CS47L35
CS47L35
or similar
CODEC



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