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LSM6DSV16BX 데이터시트(PDF) 18 Page - STMicroelectronics

부품명 LSM6DSV16BX
상세설명  iNEMO 3-axis accelerometer and 3-axis gyroscope: inertial module for UI and bone conduction with embedded machine learning core and Qvar specification
PDF  148 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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LSM6DSV16BX 데이터시트(HTML) 18 Page - STMicroelectronics

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4.4.3
TDM - time-division multiplexing interface
@ Vdd_IO = 1.8 V, T = 25 °C unless otherwise noted. Refer to Section 5.3 TDM interface for additional details.
Table 8. TDM timing values
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
BCLKf
BCLK frequency (1/tp)
WCLK = 16 kHz
2.048
MHz
BWCLKA
BCLK/WCLK frequency accuracy
-0.1
+0.1
%
BCLKj
BCLK jitter
4
ns
(peak to peak)
WCLK8
8 kHz WCLK mode
8
kHz
WCLK16
16 kHz WCLK mode
16
PDC
All clock pin duty cycle - referred to BCLK (except WCLK)
45
55
%
WST
WCLK setup time before BCLK rising/falling edge (tss1)
20
ns
WHT
WCLK hold time after BCLK rising/falling edge (ths3)
20
ns
TDMST
TDMout setup time before BCLK rising/falling edge (tss2)
15
ns
TDMHTR
TDMout hold time after BCLK rising/falling edge (ths1)
15
ns
TDMHTZ
TDMout hold time of LSB after BCLK rising/falling edge (ths2)
15
65
ns
CBCLK
BCLK pin capacitance
10
pF
CTDMout
TDMout load capacitance
60
Note:
All setup times and hold times in Table 8 and in Figure 10 are valid for BCLK polarity set to “clock on rising”.
If BCLK polarity is set to “clock on falling”, then all setup and hold times will refer to the falling edge of BCLK
instead. Please refer to Section 5.3 TDM interface for additional details.
Figure 10. TDM timing diagram
BCLK
TDMout
MSB
LSB
WCLK
tss1
t p
tss2
ths1
ths2
ths3
LSM6DSV16BX
Communication interface characteristics
DS13771 - Rev 2
page 18/148



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