ADF4377 datasheet(62/79 Pages) AD

62 / 79 page

Data Sheet

ADF4377

analog.com

Rev. 0 | 62 of 79

Figure 134.

Table 71. Bit Descriptions for REG0020

Bits

Bit Name

Description

Reset

Access

[7:6]

R020_RSV5

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV4

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

RST_SYS

Reset Digital Functions to POR State. Does not reset the SPI interface and SPI registers. This bit is not

self-clearing.

0x0

R/W

0: reset inactive. Normal operation.

1: reset active.

EN_ADC_CLK

Enable the ADC Clock. See Figure 70.

0x0

R/W

0: disabled.

1: enabled. Normal operation.

R020_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV2

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

R020_RSV1

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x21, Reset: 0x00, Name: REG0021

Figure 135.

Table 72. Bit Descriptions for REG0021

Bits

Bit Name

Description

Reset

Access

[7:4]

R021_RSV7

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

[3:0]

R021_RSV3

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x22, Reset: 0x00, Name: REG0022

Figure 136.

Table 73. Bit Descriptions for REG0022

Bits

Bit Name

Description

Reset

Access

[7:0]

R022_RSV0[7:0]

Reserved. Table 42 provides required reserved register settings.

0x0

R/W

Address: 0x23, Reset: 0x00, Name: REG0023

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