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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ADP5140WACCZ-R7 데이터시트(PDF) 48 Page - Analog Devices |
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ADP5140WACCZ-R7 데이터시트(HTML) 48 Page - Analog Devices |
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48 / 128 page  ADP5140 Data Sheet Rev. 0 | Page 48 of 128 REGULATOR 2 REGULATOR 5 REGULATOR 11 REGULATOR 1 REGULATOR 12 VIN REGULATOR 3 REGULATOR 8 REGULATOR 6 REGULATOR 7 REGULATOR 9 REGULATOR 4 REGULATOR 10 VMDW SPI_CMD1 (POWER-DOWN COMMAND) RESET STATUS FAULT Figure 90. Power-Down Sequence SPI The ADP5140 uses the SPI to communicate with the processor. The ADP5140 is always the slave and has a single input and output mode. SPI Mode 0 and Mode 3 are supported in the ADP5140. In Mode 0 (clock polarity (CPOL) = clock phrase (CPHA) = 0), SCK is low when the clock is inactive. In Mode 3 (CPOL = CPHA = 1), SCK is high when the clock is inactive. In both modes, bits are always sampled at the rising edge of the clock and driven at the falling edge of the clock. The ADP5140 detects which mode is used automatically when receiving bit streams from the host. Through the SPI, the processor can configure the ADP5140 functionalities and set the device parameters. The processor can also read back the status of the ADP5140. Refer to the SPI Register Map section for detailed information on the ADP5140 registers. |
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