STW81101AT datasheet(11/42 Pages) STMICROELECTRONICS

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STW81101

Electrical specifications

11/42

2.5

Phase noise specification

VCTRL

VCO control voltage(4)

0.4

LO Harmonic Spurious(4)

-20

dBc

VCO current consumption

VCO buffer consumption

DIVIDER by 2 consumption

DIVIDER by 4 consumption

LO OUTPUT BUFFER

Output level

dBm

Return Loss(4)

Matched to 50ohm

Current Consumption

DIV4 Buff

DIV2 Buff

Direct Output

EXTERNAL VCO (Test purpose only)

Frequency range

3.3

4.4

GHz

Input level

dBm

Current Consumption

VCO Internal Buffer

µA

PLL MISCELLANEOUS

Current Consumption

Input Buffer, Prescaler,

Digital Dividers, misc.

Lock up time (4)

40 KHz PLL bandwidth;

within 1 ppm of

frequency error

150

µs

The frequency step is related to the PFD input frequency as follows:

- fstep = fPFD for Direct Output

- fstep = fPFD/2 for Divided by 2 Output

- fstep = fPFD/4 for Divided by 4 Output

see relationship between ICP and REXT in the Circuit Description section (Charge Pump)

PFD frequency leakage (400KHz) and harmonics

Guaranteed by design and characterization.

Table 5.

Electrical characteristics (continued)

All the Electrical Specifications are intended at 3.3V supply Voltage.

Symbol

Parameter

Test conditions

Min

Typ

Max

Unit

Table 6.

Phase noise specification

Parameter

Test conditions

Min

Typ

Max

Unit

PHASE NOISE PERFORMANCE(1)

In Band Phase Noise Floor – Closed Loop(2)

Normalized In Band Phase Noise

Floor

ICP=4mA, PLL BW = 50KHz;

including reference clock

contribution

-220

dBc/Hz

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