STW81101

List of figures

5/42

List of figures

Figure 1.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2.

Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Figure 4.

Figure 5.

VCO A (Div. by 2 output) closed loop phase noise at 1.8GHz with FSTEP=200KHz

Figure 6.

VCO B (Div. by 2 output) closed loop phase noise at 2.0GHz with FSTEP=200KHz

Figure 7.

VCO A (Div. by 4 output) closed loop phase noise at 900MHz with FSTEP=100KHz

Figure 8.

VCO B (Div. by 4 output) closed loop phase noise at 1.0GHz with FSTEP=100KHz

Figure 9.

Figure 10.

Figure 11.

Reference Frequency Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 12.

VCO Divider Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 13.

PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14.

Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15.

VCO Sub-Bands Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16.

Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 17.

Start and Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 18.

Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 19.

Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 20.

Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 21.

Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 22.

SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 23.

SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24.

Differential/single ended output network in the 3.3 - 4.4GHz range

(MATCH_LC_LUMP_4G_DIFF.dsn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 25.

LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 35

Figure 26.

Microstrip line and lumped matching network (MATCH_4G_HYBRID.dsn) . . . . . . . . . . . . 35

Figure 27.

Differential/single ended output network in the 1.65 - 2.2GHz range

(MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 28.

LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 36

Figure 29.

Lumped output matching for divided by 2 output (MATCH_LC_BAL_2G.dsn) . . . . . . . . . 37

Figure 30.

LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . 37

Figure 31.

Lumped output matching for divided by 4 output (MATCH_LC_BAL_1G.dsn) . . . . . . . . . 38

Figure 32.

Application diiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 33.

VFQFPN28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40