STW81101AT datasheet(17/42 Pages) STMICROELECTRONICS

17 / 42 page

STW81101

General description

17/42

4.1.4

A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17

or 19/20) prescaler make it possible to generate output frequencies which are spaced only

by the reference frequency divided by the reference division ratio. Thus, the division ratio

and the VCO output frequency are given by these formulas:

N = B · P + A

where:

Fvco: output frequency of VCO.

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

Fref: input reference frequency.

R: division ratio of reference counter.

N: division ratio of PLL

For a correct work of the VCO divider, B must be strictly higher than A. A can take any value

ranging from 0 to 31. The range of the N number can vary from 256 to 65551 (P=16) or from

361 to 77836 (P=19).

Figure 12.

VCO Divider Diagram

4.1.5

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output

proportional to the phase error. The PFD includes a delay gate that controls the width of the

anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer

function.

Figure 13 is a simplified schematic of the PFD.

vco

⋅

() F

ref

⋅

------------------------------------------

5 bit

A counter

12 bit

B counter

To PFD

modulus

VCOBUF+

VCOBUF-

Prescaler

16/17 or 19/20

STW81101AT 데이터시트(PDF) 17 Page - STMicroelectronics

STW81101AT 데이터시트(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

데이터시트 다운로드

링크 URL