SCAS641

– JULY 2000

15

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50 ns

150 ns

100 ns

200 ns

0 ns

PWRDWN

HOST 100 MHz

HOST 100 MHz

3VMREF

3VMREF

3V66 MHz

PCI 33MHz

3V48 MHz

REF 14.318 MHz

Figure 4. Power DOWN Timing

RS1 = 33

RS1 = 33

RT1 = 49.9

RIREF = 475

RT1 = 49.9

TLA

TLB

CL = 2 pF

CL = 2 pF

Clock

Clock

HCLK

HCLK

MultSel0

MultiSel1

CDC930

VDD

NOTE A:Z(TLA) = Z(TLB) = 50 , L(TLA) = L(TLB) = 3.5’’, CL represents probe and jig capacitance.

Figure 5. Load Circuit for 0.7 V Amplitude HCLK/HCLK Bus