SPC584G80 datasheet(77/139 Pages) STMICROELECTRONICS

77 / 139 page

DS11758 Rev 6

77/139

SPC584Gx, SPC58EGx, SPC58NGx

Electrical characteristics

All the Flash operations require the presence of the system clock for internal

synchronization. About 50 synchronization cycles are needed: this means that the timings of

the previous table can be longer if a low frequency system clock is used.

8. Rate computed based on 256 KB sectors.

9. Only code sectors, not including EEPROM.

10. Time between suspend resume and next suspend. Value stated actually represents Min value specification.

11. Timings guaranteed by design.

12. AIC is done using system clock, thus all timing is dependent on system frequency and number of wait states. Timing in the

table is calculated at max frequency.

Table 42. Flash memory Life Specification

Symbol

Characteristics(1) (2)

1. Program and erase cycles supported across specified temperature specifications.

2. It is recommended that the application enables the core cache memory.

Value

Unit

Min

Typ

NCER16K 16 KB CODE Flash endurance

—

100

— Kcycles

NCER32K 32 KB CODE Flash endurance

—

100

— Kcycles

NCER64K 64 KB CODE Flash endurance

—

100

— Kcycles

NCER128K 128 KB CODE Flash endurance

—

100

— Kcycles

NCER256K

256 KB CODE Flash endurance

—

100

— Kcycles

256 KB CODE Flash endurance(3)

3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time

are possible.

—

100

— Kcycles

NDER64K 64 KB DATA EEPROM Flash endurance

250

—

— Kcycles

NDER16K 16 KB HSM DATA EEPROM Flash endurance

100

—

— Kcycles

tDR1k

Minimum data retention Blocks with 0 - 1,000 P/E

cycles

—

Years

tDR10k

Minimum data retention Blocks with 1,001 - 10,000

P/E cycles

—

Years

tDR100k

Minimum data retention Blocks with 10,001 - 100,000

P/E cycles

—

Years

tDR250k

Minimum data retention Blocks with 100,001 -

250,000 P/E cycles

—

Years

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