MPC8540 datasheet(213/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

II-1

Part II

e500 Core Complex and L2 Cache

This part describes the many features of the MPC8540 core processor at an overview level and the

interaction between the core complex and the L2 cache. The following chapters are included:

•

Chapter 5, “Core Complex Overview,” provides an overview of the e500 core processor

and the L1 caches and MMU that, together with the core, comprise the core complex.

•

Chapter 6, “Core Register Summary,” provides a listing of the e500 registers in reference

form.

•

Chapter 7, “L2 Look-Aside Cache/SRAM,” describes the L2 cache of the MPC8540. Note

that the L2 cache can also be addressed directly as memory-mapped SRAM.

The e500 processor core is a low-power implementation of the family of reduced instruction set

computing (RISC) embedded processors that implement the PowerPC architecture. This part

provides additional information about the Book E architecture as it relates specifically to the e500

core complex and specific details on how its registers are accessed.

The e500 core complex interacts with the L2 cache through the core complex bus (CCB).

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