BT817AQ-R datasheet(28/58 Pages) BRIDGETEK

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BT817A Automotive Advanced Video Engine Datasheet

Version 1.0

Document No.: BRT_000251 Clearance No.: BRT#194

framerate

passthrough, adaptive framerate

hsync

passthrough, adaptive hsync

Yes

not supported

Yes

extsync mode

Yes

extsync, HSF

Yes

framerate

extsync, adaptive framerate

Yes

framerate

Yes

extsync, adaptive framerate,

HSF

Yes

hsync

extsync, adaptive hsync

Yes

hsync

Yes

extsync, adaptive hsync, HSF

Yes

extsync mode, 2X pixels

Yes

framerate

extsync, 2X, adaptive framerate

Yes

hsync

extsync, 2X, adaptive hsync

Yes

not supported

Table 4-15 Display mode

4.6 Miscellaneous Control

4.6.1 Backlight Control Pin

The backlight dimming control pin (BACKLIGHT) is a Pulse-width Modulation (PWM) signal controlled

by two registers: REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output

frequency, the range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128.

A value of 0 means that the PWM is completely off and 128 means completely on.

The BACKLIGHT pin will output low when the DISP pin is not enabled (i.e., logic 0).

4.6.2 DISP Control Pin

The DISP pin is a general-purpose output that can be used to enable or reset the LCD display panel.

The pin is controlled by writing to Bit 7 of the REG_GPIO register, or bit 15 of REG_GPIOX.

4.6.3 General Purpose IO pins

The BT817A can be configured to use up to 4 GPIO pins. These GPIO pins are controlled by the

REG_GPIOX_DIR and REG_GPIOX registers. Alternatively, the GPIO0 and GPIO1 pins can also be

controlled by REG_GPIO_DIR and REG_GPIO to maintain backward compatibility with the

FT800/FT801.

When the QSPI is enabled in Quad mode, GPIO0/IO2 and GPIO1/IO3 pins are used as data lines of the

QSPI.

4.6.4 Pins Drive Current Control

The output drive current of output pins can be changed as per the following table by writing to

bit[6:2] of REG_GPIO register or bit[14:10] of REG_GPIOX register. Alternatively, use the SPI

command PINDRIVE to change the individual pin drive strength.

REG_GPIO

Bit[6:5]

Bit[4]

Bit[3:2]

REG_GPIOX

Bit[14:13]

Bit[12]

Bit[11:10]

Value

00b#

01b

10b

11b

0b#

00b#

01b

10b

11b

Drive

Strength

Degree

DSD1 DSD2 DSD3 DSD4 DSD1 DSD2 DSD1 DSD2 DSD3 DSD4

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