BT817AQ-R datasheet(42/58 Pages) BRIDGETEK

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BT817A Automotive Advanced Video Engine Datasheet

Version 1.0

Document No.: BRT_000251 Clearance No.: BRT#194

Address

(hex)

Bit

Reset

value

Description

302168h

REG_TOUCH_CONFIG

16 r/w

0381h

Touch configuration.

I2C address, low-power mode,

touch host mode

30216Ch

REG_CTOUCH_TOUCH4_X

16 r/o

Extended mode: touch-screen

screen X data for touch 4

302170h

REG_EHOST_TOUCH_ACK

4 r/w

Touch host mode:

acknowledgement

302174h

302184h

Reserved

- -

Reserved

302188h

REG_SPI_WIDTH

3 r/w

QSPI bus width setting

Bit [2]: extra dummy cycle on

read

Bit [1:0]: bus width (0=1-bit,

1=2-bit, 2=4-bit)

30218Ch

REG_CTOUCH_TOUCH2_X

32 r/o

Extended mode: touch-screen

screen data for touch 2 (x-

MSB16; y-LSB16)

302190h

REG_CTOUCH_TOUCH3_X

32 r/o

Extended mode: touch-screen

screen data for touch 3 (x-

MSB16; y-LSB16)

302194h

302560h

Reserved

- -

Reserved

302564h

REG_DATESTAMP

r/o

Stamp date code

302574h

REG_CMDB_SPACE

12 r/w

FFCh

Command DL (bulk) space

available

302578h

REG_CMDB_WRITE

32 w/o

Command DL (bulk) write

30257Ch

REG_ADAPTIVE_FRAMERA

1 r/w

Reduce frame rate during

complex drawing

3025ECh

REG_PLAYBACK_PAUSE

1 r/w

Audio playback control. 0: play,

1: pause

3025F0h

REG_FLASH_STATUS

2 r/w

Flash status. 0: INIT, 1:

DETACHED, 2: BASIC, 3: FULL

3025F4h

302608h

Reserved

- -

Reserved

30260Ch

REG_UNDERRUN

32 r/o

Line underrun counter

302610h

REG_AH_HCYCLE_MAX

12 r/w

Adaptive Hsync: maximum

horizontal total PCLK cycles. 0

means Adaptive Hsync is

disabled.

302614h

REG_PCLK_FREQ

16 r/w

Fractional PCLK

frequency/enable. Firmware sets

to 08A1h at boot.

302618h

REG_PCLK_2X

1 r/w

Core scan out 2-pixel data per

system clock

309000h

REG_TRACKER

32 r/w

Tracker register 0

309004h

REG_TRACKER_1

32 r/w

Tracker register 1

309008h

REG_TRACKER_2

32 r/w

Tracker register 2

30900Ch

REG_TRACKER_3

32 r/w

Tracker register 3

309010h

REG_TRACKER_4

32 r/w

Tracker register 4

309014h

REG_MEDIAFIFO_READ

32 r/o

Media FIFO read offset

309018h

REG_MEDIAFIFO_WRITE

32 r/w

Media FIFO write offset

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